Hybrid analog-to-digital converter

ABSTRACT

An analog-to-digital converter includes a first converter stage comprising a successive-approximation-register (SAR) analog-to-digital converter (ADC), the SAR ADC being configured for voltage domain quantization, a second converter stage coupled to the first converter stage to quantize residual voltages of the voltage domain quantization, the second converter stage including a ring time-to-digital converter (TDC), and a third converter stage comprising an interpolation TDC, the interpolation TDC being coupled to the second converter stage to provide further time domain quantization.

BACKGROUND OF THE DISCLOSURE Field of the Disclosure

The disclosure relates generally to analog-to-digital converters (ADCs).

Brief Description of Related Technology

Broadband communications, such as the emerging 5G wireless system, demand high speed and power efficient ADCs. Among the various ADC topologies, flash ADCs feature a high conversion rate. However, they are not suitable for applications with medium-to-high resolution due to the exponentially increased hardware and power consumption. Pipeline ADCs are suitable for medium-to-high resolution designs with moderate conversion speed. However, the pipeline architecture uses highly linear and power-hungry inter-stage amplifiers to amplify the residues of the preceding stages. This requirement prevents pipeline architectures from being adopted in high performance ADC designs.

The successive-approximation-register (SAR) ADC has become one of the most popular architectures in recent years due to its good power efficiency, lower mismatch and improved conversion rate in advanced CMOS technology. There are many techniques, such as the monotonic switching capacitor-digital-to-analog converter (CDAC) and the dynamic comparator arrays, that enhance the SAR ADC conversion speed and hence the overall performance. However, the performance of a single stage SAR ADC is generally limited by the following issues. The conversion speed degrades at high resolution. For instance, it is hard to achieve a several hundred MS/s sample rate with more than 10-bit resolution. The comparator noise, which is lower than half of the ADC resolution step, is mainly constrained by its thermal noise. When resolution increases, the power consumption of the comparator increases to suppress its noise and achieve the desirable comparison time, which degrades the overall power efficiency.

In order to meet low power and high-speed requirements, pipelined SAR ADC architectures have been adopted to address the problems outlined herein. A hybrid architecture has several advantages when compared with conventional SAR ADCs. The pipeline architecture allows each pipeline stage to operate simultaneously, accelerating the overall conversion time. The amplification stages between two pipeline stages provide sufficient gain to relax the noise requirement in subsequent stages. The hybrid architecture inherits the advantages present in different structures. For instance, employing a SAR ADC as the first stage inherits its good power efficiency and employing a flash ADC as the first stage inherits superior conversion speed. In prior designs, a pipelined SAR ADC with a multiplying DAC (MDAC) subrange quantizer suppresses noise by providing large MDAC gain. A pipelined SAR ADC with 2-bit per cycle SAR ADC as the coarse quantizer in the first stage with its resulting zero-crossing based interface achieves not only fast conversion speed, but also process-voltage-temperature (PVT) constant performance with open-loop amplifiers. However, amplification stages are still used in such architectures in order to relax the noise requirements in subsequent stages, which leads to several problems. Advanced CMOS technology in the deep submicron region presents challenges for high gain closed-loop amplifier designs due to reduced power supply voltage. Open-loop amplifiers can be considered but their gains are affected by PVT variations. Regardless of the type of the amplifier employed, large power consumption is inevitable in order to provide the desired voltage gain and linearity.

The pipelined SAR ADCs perform data conversion only in the voltage domain, and are facing increasing challenges in deep submicron CMOS technology with reduced supply voltages. For instance, as the power supply voltage is reduced in deep submicron technologies (e.g., 1.8V in 130 nm technology versus 0.8V in 22 nm technology), the voltage domain full scale is reduced, resulting in insufficient dynamic range. Therefore, this approach is not suitable for achieving fine quantization in high resolution data converter designs. Also, inter-stage amplifiers used in voltage domain pipeline topologies have stringent gain and linearity requirements. Thus, the design of high-performance voltage amplifiers becomes challenging in advanced technology.

In comparison, if the fine quantizer is implemented in the time domain, the aforementioned challenges can be almost universally avoided. In this hybrid topology, voltage-to-time convertor (VTC) works as the interface between the voltage quantizer and the time domain quantizer, and this arrangement provides good linearity with low power consumption. For instance, the linearity of the discharging based VTC is related to discharging current sources rather than the transconductance of the transistors, which results in good linearity. The voltage-to-time gain of the discharging based VTC is related to the discharging slope rather than power consumption. Therefore, it consumes less power when providing higher gain. The noise requirement of the time domain comparators is also relaxed, since it is the interval between two edges in the time domain rather than the voltage difference between small voltage residues (50 μV to 200 μV), that must be resolved. Thus, time domain quantizers are more suitable for fine quantization than voltage domain quantizers.

Time quantizers have been utilized in pipelined SAR ADCs. An architecture with pipelined SAR ADCs, a discharging-based VTC, and a time-to-digital-converter (TDC) including discharging-based delay cells has been presented for internal PVT tracking. However, the architecture suffers from a slow conversion speed caused by prolonged propagation delays through the VTC and TDC. Another architecture with a pipelined, 2-bit per cycle SAR ADC and a 2-D Vernier TDC was presented to improve the conversion speed. However, the amplifier-based VTC is adversely affected by PVT variations.

SUMMARY OF THE DISCLOSURE

In accordance with one aspect of the disclosure, an analog-to-digital converter includes a first converter stage comprising a successive-approximation-register (SAR) analog-to-digital converter (ADC), the SAR ADC being configured for voltage domain quantization, a second converter stage coupled to the first converter stage to quantize residual voltages of the voltage domain quantization, the second converter stage including a ring time-to-digital converter (TDC), and a third converter stage comprising an interpolation TDC, the interpolation TDC being coupled to the second converter stage to provide further time domain quantization.

In connection with any one of the aforementioned aspects, the analog-to-digital converters described herein may alternatively or additionally include or involve any combination of one or more of the following aspects or features. The second converter stage and the third converter stage are coupled such that the resolution of the interpolation TDC is aligned with the resolution of the ring TDC. The second converter stage includes a ring-configured delay chain. An output of the ring-configured delay chain is used to align the resolution of the interpolation TDC with the resolution of the ring TDC. The second converter stage includes a time residue generator to generate a signal indicative of a time domain residue from the ring TDC. The time residue generator is configured to extract a residual time interval from the second converter stage for the further time domain quantization by the interpolation TDC. The time residue generator includes a first D-flip-flop configured as a comparator, and a second D-flip-flop coupled to the first D-flip-flop and configured to provide a delay. The time residue generator includes a ring-configured delay chain configured to generate a periodic square wave signal, and a comparator configured to resample a lag signal from the ring TDC with the periodic square wave signal. The ring-configured delay chain is re-used in the third converter stage to avoid mismatch between the second converter stage and the third converter stage. The time residue generator lacks edge selecting logic elements. A coupling between the second converter stage and the third converter stage lacks a voltage-to-time converter. The analog-to-digital converter further includes an inter-stage converter disposed between the first and second converter stages, the inter-stage converter being configured to convert between the voltage domain to a time domain. The inter-stage converter is configured to process the residue signal of the first converter stage such that a range of the residue signal matches a full scale of the second converter stage. The first converter stage includes a continuous switching capacitor DAC (CDAC) and a voltage comparator, and The inter-stage converter includes a voltage-to-time converter (VTC), the VTC having an input coupled to the voltage comparator. The second converter stage includes a ring time-to-digital converter (TDC). The ring TDC and the VTC operate simultaneously. The analog-to-digital converter further includes a background calibration loop to align the range of the residue signal of the first converter stage with the full scale of the second converter stage. The inter-stage converter includes a CDAC discharging-based VTC with CDAC switching timed by a lap delay of the ring TDC. The residue signal has a residual voltage range equal to the full scale of the second converter stage. A system includes a set of analog-to-digital converters, each analog-to-digital converter being configured in accordance with one of the examples described herein. The set of analog-to-digital converters are disposed in a parallel, time-interleaved arrangement. The system further includes a timing skew calibration circuit configured to determine timing skew via a comparison of a difference between sampling edges with an average value of sampling edge differences. The analog-to-digital converter further includes an inter-stage converter disposed between the first and second converter stages, the inter-stage converter being configured to convert the residual voltages from a voltage domain to a time domain, and a noise shaping circuit being configured to extract a time domain residue from the second converter stage, configured to convert the time domain residue to a voltage signal, configured to perform sigma-delta noise shaping, and configured to generate references to control the second converter stage. The first converter stage includes capacitor DACs (CDACs) and comparators. The noise shaping circuit includes a phase detector, a charge pump and a sigma-delta processing unit to extract and process a time domain residue and provide feedback for controlling the CDACs. A low-pass filtered residue voltage is processed by the sigma-delta processing unit for noise shaping to update the references prior to a next fine quantizer conversion.

BRIEF DESCRIPTION OF THE DRAWING FIGURES

For a more complete understanding of the disclosure, reference should be made to the following detailed description and accompanying drawing figures, in which like reference numerals identify like elements in the figures.

FIG. 1 is a schematic view of a hybrid ADC having a voltage domain ADC stage as a coarse quantizer, a VTC as an inter-stage, and a TDC stage as a time-domain fine quantizer, in accordance with one example.

FIG. 2 depicts a schematic view of a hybrid ADC having a 2-bit per cycle SAR ADC stage as a coarse quantizer, a discharging-based VTC as an inter-stage, a two-dimension Vernier TDC stage as a fine quantizer, and a background PVT calibration loop, in accordance with one example, along with graphical and diagrammatic views of the operation of the hybrid ADC.

FIG. 3 depicts a schematic, partial view of a SAR ADC stage for use in a hybrid ADC in accordance with one example to show the generation of multiple (e.g., four) voltage residues from the 2-bit per cycle coarse SAR ADC stage and the utilization thereof to produce an input for the TDC fine quantizer stage of the hybrid ADC, as well as to show the information used for PVT calibration. Derived from the two residues, the difference between voltages V_(P1) and V_(N2) contains the residue voltage information so that the residues can be used as the VTC inputs. The differences between the voltages V_(P1) and V_(P2), V_(N1) and V_(N2) contain the full-scale information so that the residues can be used as references for PVT calibration. The full-scale value is checked in every conversion cycle to ensure that full-scale in the time domain is aligned with that of the voltage domain. Therefore, robust performance over PVT variations is guaranteed.

FIG. 4 is a schematic view of a hybrid ADC having a coarse SAR ADC stage, an inter-stage with a passive residue transfer technique, and a hybrid ring TDC-based fine quantizer stage in the time domain in accordance with one example.

FIG. 5 depicts a graphical and diagrammatic view of the signal propagation and other operations of the hybrid ADC of FIG. 4 .

FIG. 6 is a schematic view of a hybrid ADC having three pipelined stages including a SAR ADC, a ring TDC-based time-domain quantizer, and an interpolation TDC-based time-domain quantizer to provide fine time domain resolution and at a high conversion rate in accordance with another example.

FIG. 7 depicts schematic views of ring-TDC based fine quantizers in accordance with two examples, one based upon a single ring TDC, and the other based on a Vernier ring TDC. Parameters N and C represent the number of delay cells placed in one ring. Parameter M refers to the full scale of the switching-capacitor based VTC, which represents the number of laps the signal propagates in the ring before the second time residue is generated. Both examples can be implemented with internal PVT tracking. The single ring example provides faster conversion speed, while the Vernier example provides finer resolution and a larger time domain detectable range.

FIG. 8 depicts a block diagram of a hybrid ADC having a coarse SAR ADC and a time domain fine quantizer, including a ring TDC, a feedback loop, and further having a phase detector and a CDAC reference generator with sigma-delta noise shaping in accordance with one example. The residual time-interval from the ring TDC fine quantizer is captured by the phase detector and is fed back to a sigma delta signal processing unit to generate the CDAC references with noise shaping feature. The noise shaping feedback loop can be constructed with a phase detector to extract the time domain residue, a current-controlled charge pump to convert the time interval pulse into current pulses that further charge the loop filter. The voltage on the loop filter capacitor represents the fine quantizer residue and is further processed by a sigma-delta noise shaping unit to generate the CDAC references.

FIG. 9 is a graphical and diagrammatic view of an internal PVT tracking technique implemented by, and embedded in, the ring-TDC based time quantizer in accordance with one example, in which the slope of the switching-capacitor based VTC is determined by the total delay in one lap of the ring TDC and the voltage applied to the switching capacitor. This configuration automatically guarantees that the full scale of the time domain quantizer is aligned with the LSB of the voltage domain regardless of the variation of the PVT.

FIG. 10 depicts a graphical view of a timing skew calibration technique in accordance with one example, in which, in a foreground calibration mode, a low frequency ramp signal is used as the ADC input signal. The left of the figure shows an ideal case where no timing skew occurs. Since the slope of the ramp signal remains constant when the input is sampled by interleaved ADC cores, the time intervals between two adjacent sample points remain constant. As a result, the differences between two adjacent digital outputs, illustrated as Diff_12, Diff_23, Diff_34, and Diff_41 in the figure, remain the same. The right of the figure illustrates a case where timing skew occurs in the 3rd sample clock (Sample_CLK3). Since the sample edge of Sample_CLK3 is earlier than that in the ideal case, the sampled voltage of the 3rd ADC core is smaller than that in the ideal case. Hence, Dout3 becomes smaller. The change of Dout3 can be detected by detecting smaller Diff_23 and larger Diff_34.

FIG. 11 depicts a block diagram of a timing skew calibration architecture in accordance with one example, along with a timing diagram of signals processed or provided thereby.

FIG. 12 is a block diagram of an architecture of a hybrid analog-to-digital converter with voltage, current, charge, time, and/or frequency domain signal processing in accordance with one example.

The embodiments of the disclosed converters may assume various forms. Specific embodiments are illustrated in the drawing and hereafter described with the understanding that the disclosure is intended to be illustrative. The disclosure is not intended to limit the invention to the specific embodiments described and illustrated herein.

DETAILED DESCRIPTION OF THE DISCLOSURE

An analog-to-digital converter includes a hybrid pipelined topology with multi-domain signal processing, including, but not limited to, voltage, current, time, frequency and charge domain signal processing and quantization. In some cases, the architectures described herein include a first converter stage, a second converter stage coupled to the first converter stage to quantize a residue signal of the first converter stage, and an inter-stage converter disposed between the first and second converter stages. The inter-stage converter is configured to convert between a first domain and a second domain. The inter-stage converter is configured to process the residue signal of the first converter stage such that a range of the residue signal matches a full scale of the second converter stage. As examples of the multi-domain data-converters, also described are hybrid two-stage ADCs with voltage-domain SAR ADCs as a coarse quantizer and time-domain time-to-digital converters (TDCs) as a fine quantizer. The fine quantizer may either be or otherwise include a ring TDC or a Vernier ring TDC with its full-scale range automatically matched with the residue of the coarse quantizer. The discharge based inter-stage voltage-to-time converters (VTCs) allow simultaneous operation of the VTC and the TDC, achieving a higher sample rate with low power consumption.

Hybrid analog-to-digital converters with time domain quantizers (e.g., fine quantizers) are described. The hybrid converters may be used in a wide variety of systems, including communication systems, such as radio receivers. The architectures of the disclosed converters are suitable for high speed operation with high resolution and low power consumption.

The disclosed hybrid ADC architectures may include a time domain quantizer that provides fine quantization with improved power efficiency and stable performance against PVT variations. For example, when pipelined with a multi-bit per cycle SAR ADC as the coarse quantizer, the disclosed hybrid ADC (e.g., in examples without time-interleaving) achieves greater than 500 MHz sample rates and 10-bit to 14-bit resolution when implemented in 40 nm to 22 nm technologies, which enables applications for low-power broadband wireless networks.

In one example architecture (e.g., FIG. 2 ), a high sample-rate is achieved with time domain fine quantization and background PVT calibration. In another example architecture (e.g., FIG. 4 ), better power efficiency and robust operation are achieved with an embedded PVT inner-tracking technique to eliminate the need for background calibration. In another example architecture (e.g., FIG. 6 ), fast conversion speed and fine time domain resolution are achieved by employing a triple-stage pipeline architecture with two-stage time domain quantizers, combining a ring TDC and an interpolation TDC. All of the example architectures utilize a hybrid ADC architecture with time domain fine quantization techniques that include multiple aspects directed to achieving a power efficiency Figure-of-Merit (FoM) not attained heretofore.

The resolution of the time-domain assisted ADC architectures described herein can be further improved by employing a time domain noise shaping technique, an example of which is illustrated in FIG. 8 . The time domain residue of the fine quantizer is extracted by a phase detector and is fed back to the sigma-delta reference generation unit through a charge pump and a feedback buffer. Thus, the feedback gain can be easily controlled by tuning the current of the charge pump. Also, the time residue is converted to voltage through the charge pump and is further processed by a sigma-delta noise-shaping unit to generate the references used for switching the CDAC. The approach intrinsically achieves the first-order sigma-delta noise shaping for the time residual, thereby avoiding power hungry amplification.

In some cases, the disclosed hybrid ADCs include an ADC stage as a coarse quantizer, a VTC to convert the voltage residues of the coarse ADC stage to the time domain, a TDC stage as a fine quantizer, and a calibration unit that tracks PVT variation and automatically adjusts VTC gain so that the residues from the voltage domain are aligned with, or otherwise match, the full scale of the time domain quantizer over (e.g., regardless of) PVT variations.

The conversion speed of the disclosed hybrid ADCs may be improved by time-interleaving techniques. The time-interleaved ADCs include multiple identical single core ADCs that perform data conversion in parallel. The conversion speed of N time-interleaved ADCs may be N times larger than the sample rate of the single core ADC. However, without calibration of the non-overlapped clocks used to clock the interleaved ADCs, timing skews and mismatches among these clocks would cause ADC performance degradation. In the disclosed converters, a calibration technique that features simple implementation and fast convergence is provided that automatically calibrates the timing skews and mismatches to secure ADC performance. The disclosed calibration technique may be applied to the examples described below when employing time-interleaving techniques.

In one example (e.g., FIG. 2 ), a converter includes a 2-bit per cycle SAR ADC stage as a coarse quantizer, a discharging-based VTC inter-stage for voltage-to-time conversion, a 2-dimensional Vernier TDC stage as a fine quantizer and a phase-detector-based background calibration loop for VTC gain calibration against PVT variations. The number of bits, topologies, and/or other characteristics of the ADC stage, the VTC inter-stage, and the TDC stage are only illustrative and do not limit the application of the architecture to other combinations of topologies. The 2-bit per cycle SAR ADC and 2-dimensional Vernier TDC are used to improve the conversion speed. Other multi-bit per cycle SAR ADCs may also be used to achieve a desired level of performance with various power consumption and hardware. Moreover, the 2-bit per cycle SAR ADC generates a pair of voltage residues after the coarse quantization, including two input dependent voltages and two reference voltages related to the full-scale of the coarse ADC. As a result, one residue voltage may be used as the input signal of the VTC, while another residue may be used for TDC full-scale calibration to align or otherwise match the voltage-domain signal with its time-domain counterpart over PVT variations.

In another example (e.g., FIG. 4 ), a converter includes a single bit per cycle SAR ADC stage as a coarse quantizer in the voltage domain and a ring-TDC stage as a fine quantizer in the time domain. The numbers of bits, topologies, and/or other characteristics of the ADC, VTC, and TDC are only illustrative and do not limit the application of the architecture to other combinations of topologies. The ring-TDC-based fine quantizer stage is configured to convert voltage residues to time domain signals and digitize them at the same time. Utilizing a capacitor-switching technique, the Least-Significant-Bit (LSB) is aligned to the TDC full scale such that no additional PVT calibration is needed. Furthermore, the ring TDC inter-stage is used to time the VTC conversion and starts operation immediately when the VTC conversion is done with no interface involved.

In another example (e.g., FIG. 6 ), a hybrid converter includes a SAR ADC as the first pipeline stage in the voltage domain, a ring-TDC-based time domain coarse convertor with a time residue generator as the second pipeline stage, and an interpolation TDC as the third pipeline stage. The number of bits, topologies, and/or other characteristics of the ADC, VTC, and TDC are only illustrative and do not limit the applications of the architecture. The second pipeline stage operation may follow the same principle of the ring TDC-based quantizer in the aforementioned example, which guarantees the time domain full-scale auto-alignment with the sub-range from the voltage domain. Furthermore, the time domain residue after the second-stage conversion, is extracted and is sent to the interpolation TDC-based third stage. The interpolation TDC reuses the ring configured delay chain in the second stage and generates finer quantization steps by employing time interpolators. Therefore, the fine resolution in the interpolation TDC is aligned with the resolution of the ring TDC, regardless of the PVT variations. The example architecture achieves fast conversion speed and PVT robust pipeline ADC performance.

In a time domain noise shaping example (e.g., FIG. 8 ), a converter includes a coarse SAR ADC as a first stage in the voltage domain, a pipeline inter-stage, a ring TDC based time domain fine quantizer, and a time domain noise shaping circuit to perform a sigma-delta operation. The number of bits, topologies, and/or other characteristics of the ADC, VTC, and TDC are only illustrative and do not limit the application of the architecture to other combinations of topologies. The illustrated time domain noise shaping provides low power consumption, well-controlled feedback gain, and residue extraction without attenuation. The sigma-delta technique can be applied to other time domain assisted ADCs with minimal cost of hardware to improve the signal-to-noise ratio by noise shaping.

A comparison of these example architectures indicates the following: the first example architecture (e.g., FIG. 2 ) has the potential to operate at a higher sample rate because a SAR ADC stage with multiple bits per cycle is used as the coarse quantizer. The second example architecture (e.g., FIG. 4 ) features better power efficiency with reduced design complexity. The third example architecture (e.g., FIG. 6 ) has the potential to achieve finer resolution in the time domain while operating at a higher sample rate. The time domain noise shaping technique (see, e.g., FIG. 8 ) helps to achieve high resolution while maintaining low power consumption. The phase detector and charge pump employed in the noise shaping technique perform residue extraction and provide feedback for controlling CDAC references with minimal hardware.

The configuration, arrangement, and/or other characteristics of the coarse quantizer, the VTC inter-stage, and the fine quantizer are not limited to the topologies referenced above. For instance, a single bit or multi-bit per cycle SAR ADC and/or other ADC topologies, such as flash or flash with SAR ADCs, may be used as the coarse quantizer. A discharging based VTC or current starved VTC may be used as the VTC inter-stage. Moreover, a TDC with a single delay chain, Vernier delay chains, 2-D Vernier comparator arrays, and ring or Vernier ring TDCs may be used as the fine quantizer.

With reference now to the drawings, FIG. 1 shows a hybrid converter having a first converter stage 10, an inter-stage converter 11, and a second converter stage 12. The second converter stage 12 is coupled to the first converter stage 10 (e.g., via the inter-stage converter 11) to quantize a residual voltage range of the first converter stage 10. The inter-stage converter 11 is disposed between the first and second converter stages 10, 12.

The inter-stage converter 11 is configured to convert between a voltage domain and a time domain. In some cases, the first converter stage 10 operates in the voltage domain, converting from analog to digital. In such cases, the second converter stage 12 operates in the time domain, converting from time to digital. In other cases, the domains of the stages may differ in other cases.

In the example of FIG. 1 , the first converter stage 10 includes an ADC as a coarse quantizer, such that the inter-stage converter 11 includes a VTC configured to convert the residue voltage to time intervals for quantization in the time domain. The second converter stage 12 accordingly includes a TDC as a fine quantizer.

Examples of the architecture of FIG. 1 are described below in greater detail. Multiple instances of the examples may be employed in time-interleaved ADCs in some cases, in which a timing-skew calibration technique is implemented to mitigate the effect of time-interleaving clock mismatches. The operational aspects of the disclosed architectures and the timing-skew calibration technique are also described below.

The hybrid converters described herein may have more than two converter or quantizer stages. Thus, in other cases, one or more intermediate converter stages may be disposed between the first converter stage 10 and the second converter stage 12. An example having a number N of pipelined stages is described and shown in connection with FIG. 10 below.

FIG. 2 illustrates an ADC having an architecture in accordance with one example. The ADC in this example includes a 2-bit per cycle SAR ADC stage, a discharging-based VTC (in this cases, units 27, 28), a 2-dimention Verner TDC, and a background PVT calibration loop. The topologies, configuration, and/or other characteristics of the SAR ADC, VTC and TDC elements may differ from the example shown.

In operation, clock signal CLK_(s) turns on sample switches 38 and initiates SAR logic unit 25. In order to attain better sampling linearity at a high sample rate, bootstrapped switching and bottom-plate sampling may be employed in the architecture. When the sampling switches 38 are enabled, differential input signals, InputP and InputN, are sampled to a first capacitor-digital-to-analog converter (CDAC1) 20 and a second capacitor-digital-to-analog converter (CDAC2) 21. When the sampling switches 38 are disabled, the conversion phase begins and the zero-crossing signals are generated at the CDAC top plate by switching the capacitors. Comparators Cmp₁₋₃ 22, 23, 24 detect the zero-crossing signals, determine the subrange, and generate the finer zero-crossing signals. After a certain number of conversion cycles, the voltage residues have become smaller than the least significant bit (LSB) of the voltage-domain quantizer and are ready to be sent to the inter-stage VTC units 27, 28 for the next pipelined operation. Then, the SAR logic unit 25 enables each of VTC₁₋₂ 27, 28, while the CDACs 20 21 hold the voltage residues. After operation of the VTC units 27, 28 is completed and the time signals are generated for the TDC, the coarse SAR ADC is reset and ready for converting the next sampled data.

During the operation of the VTC₁₋₂ units 27, 28, identical current sources are applied to discharge the voltage residues that are held by the CDACs 20 21. Therefore, these voltage residues discharge at a certain speed and finally cross a pre-set threshold voltage. Crossing detectors are used to detect the moment that the threshold is crossed by the discharged residues and the rising edges are generated when the crossings occur. These rising edges are then sent to a TDC input MUX 29 to determine which edge arrives first. After the comparison, the leading edge is sent to a slow delay line 33, and the lagging edge is sent to a fast delay line 31. The other two edges that have a certain relationship to the leading and lagging edges as well as the full-scale information are sent to corresponding calibration delay lines 30, 35 for full-scale calibration against PVT variations.

The 2-D Vernier TDC, used as the fine time quantizer, includes the two delay lines 31, 33 with slightly different delays and a 2-D comparator array 37. The time interval between the leading and lagging edges is quantized by interpolating the position where the lagging edge propagating in the fast delay line 31 catches the leading edge propagating in the slow delay line 33. Once this “catching position” is detected by the comparator array 37, the TDC stops the quantization process in order to save power. The outputs of the TDC, which may be thermometer coded, are sent to code a mapping circuit 36, which converts the data to binary codes which are then combined with the binary codes obtained from the coarse SAR ADC.

The PVT background calibration loop includes two calibration delay lines 30, 35, two phase detectors 32, 34, and delay line bias control circuits. As mentioned before, there are four voltage signals generated from the 2-bit per cycle SAR ADC. Examples of the quantitative relationships of the signals are shown in FIG. 3 . Two of them are chosen as the VTC inputs that further generate the TDC inputs because they contain the zero-crossing information. The other two signals may be used for calibration because their differences to the VTC inputs are a quarter of full-scale of the subrange. By configuring the total delay of the calibration delay lines as a quarter of the full-scale length, the calibration signals at the end of calibration lines 30, 35 may be precisely set as the delays that the TDC inputs propagate in the fast and slow delay lines 31 33, respectively. The phase detectors 32, 34 check their phase differences at the end of every conversion cycle and use the results as a closed-loop feedback to tune the bias currents of the delay lines 30, 35.

FIG. 4 depicts a hybrid ADC in accordance with another example. The hybrid ADC in this case includes a one-bit per cycle SAR ADC stage as the coarse quantizer, an inter-stage VTC with passive residue transfer, and a hybrid time domain quantizer stage using a ring TDC as the fine quantizer. The configuration and/or other characteristics of the SAR ADC, the inter-stage VTC and the TDC may vary from the example shown.

In the sampling phase, sample switches 43 are turned on by clock signal CLK_(s). As mentioned before, bootstrapped switching and bottom-plate sampling may be used to attain better sampling linearity at high sample rate. The 1-bit per cycle SAR ADC employs a single comparator 41 and a single CDAC 40 to maximize the power efficiency and avoid mismatches in the first stage. The drawback is that the conversion speed of the first stage is low. However, in the subsequent stage, VTC operation and fine quantization are operating simultaneously in a pipelined manner. In addition, the interface between the VTC and the TDC is eliminated. These features increase the overall conversion speed and thus improve the figure-of-merit (FoM) of the entire hybrid ADC.

When SAR ADC conversion is done, SAR logic unit 42 initiates the passive inter-stage. In this case, the passive inter-stage includes transfer switches 44 and transfer capacitors 45. When transfer switches 44 are turned on, the voltage residues from the first stage are directly sampled to the top plates of the transfer capacitors CT 45. After the residue sampling is done, the first stage SAR ADC is ready for the next sampling phase.

The sampled residues are then shared with the capacitor arrays 46 in the second stage and level shifted by the switching capacitor. The passive inter-stage is utilized for three reasons. First, no power-hungry amplifier is needed and thus the noise requirement is much relaxed in the time domain quantizer. Second, the gain of the inter-stage transfer function is only determined by the capacitance ratio, which is insensitive to PVT variations. Third, the passive residue transfer stage achieves good power efficiency.

The second stage is or includes a ring-TDC-based hybrid time domain quantizer. In this example, the ring-TDC-based hybrid time domain quantizer includes a ring TDC 50, a TDC-controlled capacitor array 46, a continuous-time comparator (CT Cmp.) 49, and a sub logic circuit unit 47. After the residues from the first stage are sampled and level shifted, the sub logic unit 47 sends a start signal to a sub CDAC 46. When the start signal is received, the sub CDAC 46 switches a unit capacitor from Vref to ground, resulting in the top plate residue voltage switching down one LSB. Meanwhile, the start-signal propagates in the ring TDC 50. When the start signal returns to the starting point in the ring 50, the sub logic unit 47 generates another switching signal and the residue on the CDAC 46 is switched one LSB down again. The process results in a ramp-down signal for the voltage residue and the ramp-down slope is determined by the total delay of the ring TDC 50. On the other hand, the top plates of the sub-CDAC 46 are connected to a continuous-time comparator 49. Similar to the zero-crossing detector in the aforementioned discharging VTC, the continuous-time comparator 49 generates a rising edge once the ramp-down signal crosses another residue voltage obtained from the coarse quantizer. After that, the comparator output is sent to another line in the ring TDC 50. With the generated two time-domain edges, the TDC comparison is automatically initiated. The ring TDC 50 operates in a manner similar to that of a conventional TDC except that the signals propagate in a delay line configured in a ring, and the process repeats once the starting point is reached. The ring configuration permits a larger detectable range with less delay cells and thus minimizes the device mismatches due to the reduced size and more compact layout. When the crossing of two signals is detected by the comparators in the TDC, the time domain conversion is completed.

There are two types of time domain quantization in the second stage. The first type is implemented using the ring TDC 50, the sub-CDAC 46, and the continuous-time comparator 49. During the process, the CDAC switching signal propagates and circulates in the delay line of the ring TDC. Each time the switching signal propagates one lap in the ring TDC 50, the residue voltage stored on the sub-CDAC 46 is switched down with a step size of 1 LSB. Because the switching of the sub-CDAC 46 is timed by the delay of the ring TDC 50, the full scale of the time domain quantizer matches, e.g., is set to be equal to, the delay that occurs in one lap in the ring TDC 50. Therefore, the residue voltage stored on the CDAC 46 is gradually switched down to approach another residue voltage (V_(TH) of the crossing detector). The crossing position is detected by continuous-time comparator 49. The residue quantization may be done by counting the number of unit capacitors that have been switched before the crossing event occurs. Moreover, the continuous-time comparator is configured with lower bandwidth compared to the switching step frequency. The crossing point detected is actually very close to the crossing point that occurs when discharging with a current source, as shown in FIG. 5 . Therefore, the output of the continuous-time comparator 49 may be treated as the output of a discharging VTC. Therefore, the residues of the CDAC switching are linearly transferred to the time-domain signals. As depicted in FIG. 5 , the residues prior to the crossing event are equal to the voltage difference between the fixed residue voltage (V_(TH) of the crossing detector) and the voltage stored on the CDAC that are switched down every cycle. The continuous comparator is configured with good linearity, as a result of the reduced bandwidth. As a result, the voltage residue may be linearly transferred to time domain as shown in FIG. 5 . The switching signal, the first of the two rising edges prior to the crossing event (see the two rising edges encircled with the label “Time residue” in FIG. 5 ), represents the voltage residue before the last switching, while the crossing detector output (the second of the two rising edges in the circle) denotes the crossing point (V_(TH) of the crossing detector).

The second type of time domain quantization is implemented using the ring TDC 50. When the output of the continuous comparator 49 is fed to another line in the ring TDC 50, it creates a new pair of time domain signals as well as the switching signal before the crossing occurs. Since the switching signal has been propagating in the ring TDC 50, the comparison automatically begins when output of the continuous-time comparator 49 is received by the ring TDC 50. The conversion resolution of the ring TDC 50 is determined by the delay of the unit delay cell. In summary, the time domain quantizer is able to automatically switch from coarse conversion mode to fine conversion mode, while converting voltage residues to time domain signals.

FIG. 6 depicts a hybrid ADC in accordance with another example. The hybrid ADC in this case includes a first pipeline stage in the voltage domain with a SAR ADC, a second pipeline stage with a ring TDC-based time domain quantizer, and a third pipeline stage with an interpolation TDC-based quantizer. The ring TDC-based time domain quantizer may include a time residue generator. The configuration and/or other characteristics of the three pipeline stages may vary from the example shown.

During the sampling phase, clock signal CLK_(s) turns on sample switches 60 and initiates SAR logic unit 63. Bootstrapped switching and bottom-plate sampling can be employed for better sampling linearity. Differential input signals, InputP and InputN, are sampled at the capacitor-digital-to-analog converter CDAC 61. When the sampling phase is completed, the coarse conversion begins in the first-stage SAR ADC. Comparator 62 detects the polarity of the voltage residues stored on the top plate of the CDAC 61 and sends comparison results to the SAR logic 63. Then, the SAR logic 63 sends corresponding control signals to the CDAC 61 to generate the next residue. This procedure repeats until all bits in the SAR ADC are converted. After the SAR ADC conversion is completed, the voltage residue is passively transferred from the CDAC 61 in the first stage to the sub-CDAC 65 in the second stage via inter-stage switches 64. The inter-stage switches 64 are clocked by CLKT that is generated by the SAR logic 63 after the SAR conversion is completed. The residue transfer technique between the pipeline stages may vary from the example shown.

In the second stage, the voltage residue is stored on the top plate of the sub-CDAC 65. In operation, a unit capacitor C_(LSB) in the sub-CDAC 65 is continuously switched down and the switching is timed by the lap delay of the ring-configured delay chain 66. When the ring TDC conversion starts, T_(p) generated by switching signal CLK1 and is sent to the input of the ring configured delay chain 66 for propagating through the delay chain 66. Each time T_(p) reaches the starting point of the ring 66, it triggers sub-logic circuit 68 to generate a control signal that switches the sub-CDAC 65. The control signal of the sub-CDAC 65 switches one unit capacitor from high reference to low reference, causing the voltage residue stored on the top CDAC to decrease gradually, while the voltage residual stored on the bottom CDAC gradually increases toward the crossing-point. After a certain number of laps that T_(p) has propagated in the ring, the residues stored on the sub-CDACs 72 eventually cross each other. The cross detector 67 is then triggered by the residue crossing and generates a new rising edge T_(n). The time spent for this process, i.e., the time interval between T_(p) and T_(n) represents the residual magnitude in the time-domain. Furthermore, Tn and lap counting signals Cnt are sent to time residue generator 69 to extract and store the second stage's residue for further quantization in the third stage.

To extract the time residue, T_(n) is resampled with a lap counting signal Cnt. In this example, Cnt is directly generated from the ring-configured delay chain. So the lap counting signal Cnt is a periodic square wave signal whose period equals to one lap-delay of the ring, as depicted in FIG. 6 . Therefore, a D-flip-flop performs the function of a comparator at each rising of Cnt and eventually, the rising edge that immediately follows T_(n) is selected as the lag signal of time residue TR_(n). The lead signal of time residue TR_(p) is generated by T_(n) plus a D-flip-flop delay to match the delay of TR_(n).

With the time domain residue generator of this example including two D-flip-flops, the complex edge selecting logic in past two-step TDC designs is avoided. The input dependent offset caused by mismatches among the selecting logic is also eliminated. Thus, the precision of the third stage TDC is guaranteed without the need of background calibration. The time residue generation technique is only depicted as an example and is not limited to the implementation described above.

The quantization results are obtained by counting the number of laps before T_(n) is triggered. Then, the counting results are sent to encoder 70 and restored by output register 73.

In the third stage, the delay chain 66 from the second stage is reused to eliminate the delay mismatch between these two stages. The signal TR_(p) is sent to the input of the delay chain 66 for propagation and all the resulted output signals from the delay units are sent to an interpolator 71 to create further (e.g., finer) quantization steps. In this example, the time interpolator 71 includes several cascading stages of phase interpolation (PI) units 74, while each stage produces one additional interpolated signal between two adjacent time signals from the delay chain. Therefore, the quantization step is halved after each stage in the interpolator. For instance, for a delay chain that includes eight delay cells, the quantization step is ⅛th of the time domain full scale and three bits are quantized after arbiter comparison. After one stage of time interpolator 71, the original eight outputs from the delay chain become 16 signals, so the quantization step becomes 1/16th of the time domain full scale and one additional bit is quantized.

In this example, each phase interpolator unit 74 includes two identical inverters as an input stage and one follow-up inverter as an output buffer. Outputs of the two input inverters are directly tied together so the output slope is driven by transfer curves of both inverters. By balancing the delays in the two inverter stages, the threshold-crossing point of the resulted signal will fall at the center of the time interval between two inputs with acceptable error. After the output stage, three outputs are generated with the same slope when the interpolated signal is in the middle of the two original inputs.

The circuit implementation of the time domain interpolator described above is one example. Other time domain interpolators may be used.

Because the fine quantization step is a fractional quantization step of the previous stage, the ratio remains constant regardless of PVT variation, producing PVT robustness without additional calibration. Then, the interpolator 71 outputs are compared with another input TR_(n) in the arbiter array 72. The time residue is then quantized by the arbiter outputs with further (e.g., finer) resolution. Then, the arbiter outputs are subtracted from the lap counting outputs of the second stage to obtain the final quantization results. All digital bits are then sent to the output register 73 for data resampling.

In other cases, further examples may include any one or more of the components, features, elements, and/or other aspects of the example of FIG. 6 in combination with any one or more of the components, features, elements, and/or other aspects any of the other examples described herein. For instance, any of the converters described herein may include a noise shaping circuit configured to extract a time domain residue from a second converter stage, convert the time domain residue to a voltage signal, perform sigma-delta noise shaping, and generate references to control the second converter stage.

FIG. 7 depicts two examples of the time domain quantizer in greater detail. In one example, a single ring quantizer 52 includes one delay line with the resolution determined by the unit delay τ and the full range of the time quantization is aligned with the residual range in the voltage domain. Due to the reuse of the hardware in the ring configuration, the full range of the ring TDC may be as large as needed, and is limited only by the size of the memory that stores the outputs and the corresponding conversion time. If the signal propagates in the ring for M laps and k unit delay cells before the crossing event occurs, the detected time is equal to (MN+k) τ, where N is the number of unit delay cells in one lap in the ring.

In the other example, a Vernier ring quantizer 53 includes two slightly different delay lines. The resolution is determined by the difference between their unit delay cells, namely, τ_(s)−τ_(f), where τ_(s) and τ_(f) denote the unit delays in the slow line and fast line, respectively. Again, the full range of the Vernier TDC is not limited and may be aligned with the residual range in the voltage domain. If the signal propagates in the Vernier ring for M laps and k unit delay cells before the signal in the fast line catches the signal in the slow line, the detected time is equal to (MN+k)(τ_(s)−t_(f)). When compared with the single ring quantizer 52, the Vernier ring quantizer 53 has improved resolution (τ_(s)−τ_(f)) that cancels the first-order mismatches under PVT variations because all the delay cells are built using identical topologies. The drawback of the Vernier quantizer is the prolonged conversion time with the reduced time steps. When compared with prior art VTC and TDC schemes, the two examples shown in FIG. 6 have several distinct advantages, including, for instance, fine resolution, a large conversion range, less hardware and the elimination of a highly linear inter-stage VTC, etc. In addition, the single ring quantizer 52 features a fast conversion rate, while the Vernier quantizer 53 provides fine resolution.

The configuration of the Vernier ring TDC of the disclosed converters may vary from the examples shown and described herein. Further details regarding Vernier ring TDCs for use in the disclosed converters are provided in U.S. Pat. No. 8,138,958 (“Vernier Ring Time-to-Digital Converters with Comparator Matrix”), the entire disclosure of which is hereby incorporated by reference. Other types of ring-based converters may be used, including, for instance, the converters described in U.S. Patent Publication No. 2008/0069292 (“Gated Ring Oscillator for a Time-to-Digital Converter with Shaped Quantization Noise”), the entire disclosure of which is hereby incorporated by reference.

FIG. 8 illustrates a hybrid ADC with a time domain noise shaping technique for high resolution applications. The hybrid ADC includes a coarse SAR ADC, a pipeline inter-stage, a time domain fine quantizer based on the ring TDC design, and a time domain noise shaping circuit to extract the time domain residue and perform the sigma-delta noise shaping. The configuration and/or other characteristics of the SAR ADC, the inter-stage, the TDC, and the noise shaping implementation may vary from the example shown.

The coarse SAR ADC samples the differential input onto CDAC 80 and starts coarse conversion with comparator 81. The coarse conversion is the same as the process described in the aforementioned examples. After coarse conversion is completed, the voltage residue from the first stage is transferred to the fine quantizer via the pipeline inter-stage. The inter-stage can be either an amplifier to provide pipeline gain, or a passive switch to save power. Then, the sub-CDAC 82 receives the residue and the fine quantization in the time domain is initiated. The fine conversion is also similar to that described in the aforementioned ring TDC examples. After the cross detector 83 detects the zero-crossing point, the time residue is generated. The arbiter array 84 in the ring TDC quantizes the time domain residue and produces the final digital outputs.

Because the time domain quantization is performed by comparing the start signals of the ring TDC 85 with the crossing signal generated by cross detector 83, which are two inputs of the ring TDC, the time domain residue is then represented by the difference between these two inputs after the comparison in the final lap. Therefore, the residue can be extracted by employing phase detector 86. The phase detector 86 is implemented so that it can detect the rising edge of the crossing signal and the nearest rising edge in ring TDC 85 after the crossing signal occurs. Then, the output of phase detector 86, which is a voltage pulse, represents the time residue that is smaller than the fine quantization step. In the case where the quantization step is too small to be detected by phase detector 86 (e.g., when quantization step is smaller than 10 ps), the output of phase detector 86 becomes the time residue plus a fixed time offset. The time offset is determined by the response speed of phase detector 86, which is a fixed value. The static offset can be removed digitally afterwards. Then, the pulse generated is used to drive charge pump 87. The charge pump 87 performs multiple functions: (1) charge pump 87 provides feedback gain that is controlled by the charging current; (2) charge pump 87, together with the loop filter, works as an accumulator to accumulate all the previous residues (the voltage output of the charge pump represents the accumulation result of the time residual and is fed back to the fine quantizer); and (3) charge pump 87 converts the time domain residue into a voltage that can is further processed by the sigma-delta processing unit for noise shaping.

The output voltage of charge pump 87 is sent to feedback buffer 88 followed by the sigma-delta noise shaping process unit. The noise shaping unit employs sigma-delta algorithm to generate the references for switching the CDAC. By employing different sigma-delta algorithm, various orders of sigma-delta processing can be adopted. Then, the output voltage of the CDAC reference generator is switched by the sub-CDAC prior to the next conversion which performs the residue subtraction. By repeating this process in each sample cycle, the sigma-delta noise shaping is achieved. A SNR improvement of 4 dB to 8 dB can be achieved at a cost of lower signal bandwidth or duplicated hardware, depending on the over-sample ratio and the orders of sigma-delta algorithm.

FIG. 9 illustrates a PVT inner tracking and compensation technique in accordance with one example. A useful aspect of the technique involves the simultaneous operation of the VTC and TDC. When the VTC is converting the residual voltage to the corresponding time intervals, the TDC may start the conversion simultaneously without waiting for the completion of the voltage-to-time conversion. The VTC transfer function is determined by the slope of the ramping down signal generated by the switching capacitors. As explained herein, the slope is determined by the full-scale of the voltage residual, the number of fine quantization steps, and the lap length of the ring TDC 50. In other words, the slope is dependent on the step size of the switching capacitor that is set exactly to the length of the LSB in the voltage domain. Consequently, the time domain resolution is always aligned to that of voltage domain without complicated calibration loops. This innovative scheme automatically guarantees the performances of the proposed ADC under PVT variations, which have been a dilemma in all prior-art ADC designs.

The aforementioned ADCs may be time-interleaved to achieve higher sample rate. Interleaving a number N of identical ADC cores may increase the conversion rate by N times. The clock at the desired sample frequency is first divided by N times to create N non-overlapping sample clocks with uniform phase delay. As a result, ADC cores sample the input in a sequence controlled by the multi-phase clocks. Each core still operates at 1/N overall sample rate. Their digital outputs are resampled through a multiplexer at higher frequency to reconstruct the final outputs. The main challenge of the time-interleaving technique lies upon the clock skews among the N sub-sample clocks. Any mismatches among the multi-phase clocks may greatly degrade the ADC performance. The higher the ADC resolution is, the less tolerance on the clock, the skew will have.

To mitigate the clock skew or mismatch problem in the time-interleaving ADCs, a calibration technique with fast convergence may be used. Because the timing skew error is generally larger than the effect of ADC quantization error and other noise, the timing skew may be detected by analyzing the ADC output response to a ramp input.

FIG. 10 depicts an example of the calibration technique. The ideal system without timing skew is shown on the left side. Because the time interval between each two adjacent sample points are the same, the difference between adjacent sampled voltages, labeled as Diff_12, Diff_23, Diff_34, and Diff_41 is identical. On the right side of FIG. 8 , in presence of the timing skew, the sample edge of Sample_CLK3 is earlier than that in the ideal case, as an example to illustrate the operation of the technique. As a result, Diff_23 decreases and Diff_34 increases from their ideal values. To measure the change of Diff_23 and Diff_34, a reference that is not affected by timing skew is introduced. The reference may be set as the average value of Diff_12, Diff_23, Diff_34, and Diff_41 because the time interval between one sample edge of Sample_CLK1 and the next sample edge of Sample_CLK1 is not affected by the timing skew. The reference may also be set manually if the slope of the input ramp signal is given. Comparing Diff_12, Diff_23, Diff_34, and Diff_41 with the reference, the timing skew may be determined, and a bang-bang calibration may be performed by simply increasing or decreasing the time interval between the two clock edges, which may be done by tuning respective delay lines inserted on the multi-phase clock paths.

In order to minimize the measurement errors, a large number of samples may be collected to calculate the averaged values of Diff_12, Diff_23, Diff_34, and Diff_41. Unlike random noise, timing skew errors are often time-invariant, and thus the direction for tuning the phase delays remains invariant over a period of time.

FIG. 11 depicts a timing-skew calibration implementation in connection with an example of time-interleaved ADCs. In this case, an interleaved by 4 architecture is shown as an example. In the time-interleaved architecture, four single-core ADCs sample the input sequentially. The digital output of each single-core ADC is first processed by the embedded window detector to determine if the output is suitable for timing-skew estimation. A flag signal is generated if the output is suitable for estimation and the timing-skew calibration logic is enabled. After timing-skew estimation, the calibration control signals are sent to corresponding tunable delay cells to adjust the sample edge of the interleaved ADCs. The calibration procedure repeats until the timing-skew error is compensated.

In the example of time-interleaved ADCs with embedded timing-skew calibration depicted in FIG. 11 , a clock generator 90 receives a full-speed sample clock and generates sample clocks for each single-core ADC in sequence. After conversion by ADCs 94, 95, 96, the digital outputs of the ADCs are processed by window detectors 97, 98, 99 to determine if the output is suitable for timing-skew estimation. A digital multiplexer 100 receives digital outputs from individual single-core ADCs and generates an overall digital output. Finally, a timing-skew estimator 101 collects the timing-skew information from the digital output and sends control signals to tunable delay cells 91, 92, 93 to compensate for the timing skews.

FIG. 12 depicts a hybrid analog-to-digital converter architecture with a number N of pipelined stages in accordance with one example. Each stage in the pipeline may be configured to implement signal processing in a respective domain, including, without limitation, the voltage, current, charge, time, and frequency domains. For instance, any one of the stages may be configured as a voltage domain quantizer or a time domain quantizer as described herein. The architecture of FIG. 12 depicts various options for the domain of each quantizer stage.

In operation, an analog input signal in a respective domain is provided to a quantizer stage of the first pipelined stage. A digital representation of the analog input signal is provided as an output signal by the last stage, e.g., pipelined stage N. Any number of intermediate stages (e.g., zero or more) may be included in between.

Each pipelined stage includes a quantizer stage and an inter-stage domain transfer unit (or other inter-domain converter) to which a residue from the quantizer stage is provided. Each quantizer stage implements quantization in one of the domains, e.g., voltage, current, charge, time and frequency. The inter-stage between two successive stages transfers the residue from the previous stage to a signal type of the next stage. As described herein, the range of the residue is processed to match the full scale of the next stage.

In this example, with an input signal in one of the various domains, quantizers 01, 03 in each pipelined stage may be configured in accordance with the input signal type and desired performance characteristics (e.g., as described herein). Inter-stage domain transfer units 02, 04 are used between two successive pipelined stages to transfer the residue from the previous stage to a full-scale signal of the type in accordance with the domain of the next stage.

The various analog-to-digital converters with time domain fine quantizers described herein may be considered as examples of the hybrid data converter architecture depicted in FIG. 12 . By selecting the proper signal types with the best power efficiency figure-of-merit (FoM) for each quantization stage, the disclosed hybrid converter architecture is capable of achieving the best FoM for high speed, high resolution and low power data-converter applications.

Described above are hybrid converters that combine ADC and TDC stages for high performance operation either with or without time-interleaved architectures. The hybrid converters include a coarse quantizer, a fine quantizer, and inter-stage circuitry. The hybrid converters may have any one or combination of the following features. In one hybrid pipelined ADC architecture, a high conversion rate is achieved by using a pipelined architecture, with inter-stage requirements relaxed due to the reduced full scale of residue by the voltage domain coarse quantizer, and high resolution due to the use of a time domain fine quantizer. Such hybrid ADC architectures may use one or more voltage domain converters (ADCs) as the coarse quantizer (first stage), one or more voltage-to-time converters (VTCs) as the inter-stage, and one or more time domain convertors (TDCs) as the fine quantizer (second stage). Alternatively, a hybrid converter includes time domain convertors as the coarse quantizer (first stage) and voltage domain convertors as the fine quantizer (second stage). This approach may be useful for applications with direct time domain inputs. In other cases, the hybrid converter includes multiple voltage domain convertors and time domain convertors in other sequences of implementation.

With one or more voltage domain convertors as the coarse quantizer and one or more time domain convertors as the fine quantizer, a wide variety of types of ADCs or ADC architectures may be used for the coarse quantizer, including, for instance, a 1-bit per cycle SAR ADC, a 2-bit per cycle SAR ADC, a multi-bit per cycle SAR ADC, a sigma-delta SAR ADC, a flash ADC, a flash ADC followed by a SAR ADC, a flash ADC followed by a multi-bit per cycle SAR ADC, a pipelined ADC cascading ADCs of the aforementioned or other types, a hybrid ADC operating in voltage domain and including any of the aforementioned or other ADCs, or in any combination thereof.

A wide variety of types of VTCs or VTC architectures may be used, including, for instance, a discharging based VTC, a current starved VTC, a switching capacitor based VTC that employs a CDAC and a crossing detector to convert the voltage residue to an interval in time domain, a dynamic amplifier based VTC, and a hybrid VTC that converts voltage domain signals to time domain signals, and includes any of the aforementioned or other VTCs, or in any combination thereof.

A wide variety of types of TDCs or TDC architectures may be used for the fine quantizer, including, for instance, a flash TDC with a single delay line, a Vernier TDC with two delay lines, a Vernier TDC with a 2-D comparator array, a single ring TDC with a single delay line configured in a ring, a Vernier ring TDC with two delay lines configured in a couple of rings, a hybrid TDC operating in the time domain and including any of the aforementioned or other TDCs, or in any combination thereof.

Any one of the disclosed converters may be configured to implement a timing-skew calibration technique for time-interleaved ADCs that detects the timing-skew by calculating the differences between digital outputs of each two adjacent ADC single cores, sampling the same ramp signal, and comparing them with a timing-skew-free reference value. The calibration technique may be implemented by circuitry including, for instance, a built-in ramp signal generator that generates a reference input signal for the foreground calibration process (e.g., the slope of the ramp signal may be programmed in accordance with the calibration); pre-set ADC core identification bits that identify the source of each digital output, which may be useful when locating the timing skew error manually, one or more digital processing circuits configured to calculate the differences between each of two adjacent digital outputs, store the calculated information, average acquired information, and detect timing-skew error, a timing-skew-free reference indicator (e.g., the reference may be set as the average value of all acquired differences or be input manually when the slope of the input ramp signal is known), and tunable delay cells configured to control the sample point of each ADC single core. These delay cells may either be automatically tuned via closed-loop calibration circuits or be tuned manually when the off-chip calibration process is conducted.

In some cases, a hybrid pipelined converter includes ADC and TDC architectures to achieve a high conversion rate, a discharging-based VTC for good inter-stage linearity, and PVT background calibration utilizing dual-residue detection to determine the full scale of the TDC. In such cases, voltage domain convertors may be used as the coarse quantizer (first stage), and time domain convertors may be used as the fine quantizer (second stage), including, for instance, a multi-bit per cycle SAR ADC as the coarse quantizer, discharging-based VTCs as the inter-stage voltage-to-time converters, and a 2-dimensional Vernier TDC as the fine quantizer. Alternative or additional quantizer and converter types and architectures may be used in other cases.

The hybrid pipelined converter may include a PVT background calibration circuit that utilizes the dual-residues available from, e.g., the multi-bit per cycle SAR ADC. The PVT background calibration circuit may be configured to implement a technique that includes or utilizes, for instance, generation, by the coarse SAR ADC, of two or more voltage residues that contain information of inputs and the subrange full scale, transfer of the generated voltage residues to time domain intervals, detection, e.g., close-loop calibration circuits, of the full-scale information generated by the coarse SAR ADC, and tuning, either with analog or digital tuning techniques, of the TDC resolution in accordance with the detected full-scale information.

In some cases, a hybrid pipelined converter includes a single channel SAR ADC and a ring TDC with embedded voltage-to-time functionality to provide superior power-to-speed efficiency. High resolution may be provided due to the wide detection range of the ring TDC. In such cases, PVT inner-tracking may also be provided because the switching capacitor VTC is driven by the ring TDC. Voltage domain converters may be used as the coarse quantizer (first stage), and time domain converters may be used as the fine quantizer (second stage), including, for instance, an ADC in voltage domain as the coarse quantizer, a switching capacitor based VTC that employs a CDAC and a crossing detector to convert the voltage residues to the time intervals, a ring TDC as the fine quantizer, and a PVT inner-tracking scheme that utilizes both the switching capacitor VTC and the ring TDC.

The TDC may be or include, for instance, a single ring TDC with a single delay line configured in a ring, a Vernier ring TDC with two delay lines configured in a couple of rings, a hybrid TDC operating in time domain and including any of the aforementioned or other TDCs, or in any combination thereof.

The PVT tracking technique may utilize or otherwise include, for instance, a CDAC and a crossing detector to generate time intervals and digitize the time intervals simultaneously, a ring TDC configured to control the CDAC switching so that the switching step is correlated with the full scale of the residue signal, and feeding an output of the crossing detector to the ring TDC so that the time domain conversion may be started without additional amplification interface.

The present disclosure has been described with reference to specific examples that are intended to be illustrative only and not to be limiting of the disclosure. Changes, additions and/or deletions may be made to the examples without departing from the spirit and scope of the disclosure.

The foregoing description is given for clearness of understanding only, and no unnecessary limitations should be understood therefrom. 

What is claimed is:
 1. An analog-to-digital converter comprising: a first converter stage comprising a successive-approximation-register (SAR) analog-to-digital converter (ADC), the SAR ADC being configured for voltage domain quantization; a second converter stage coupled to the first converter stage to quantize residual voltages of the voltage domain quantization, the second converter stage comprising a ring time-to-digital converter (TDC); and a third converter stage comprising an interpolation TDC, the interpolation TDC being coupled to the second converter stage to provide further time domain quantization.
 2. The analog-to-digital converter of claim 1, wherein the second converter stage and the third converter stage are coupled such that the resolution of the interpolation TDC is aligned with the resolution of the ring TDC.
 3. The analog-to-digital converter of claim 1, wherein: the second converter stage comprises a ring-configured delay chain; and an output of the ring-configured delay chain is used to align the resolution of the interpolation TDC with the resolution of the ring TDC.
 4. The analog-to-digital converter of claim 1, wherein the second converter stage comprises a time residue generator to generate a signal indicative of a time domain residue from the ring TDC.
 5. The analog-to-digital converter of claim 4, wherein the time residue generator is configured to extract a residual time interval from the second converter stage for the further time domain quantization by the interpolation TDC.
 6. The analog-to-digital converter of claim 4, wherein the time residue generator comprises: a first D-flip-flop configured as a comparator; and a second D-flip-flop coupled to the first D-flip-flop and configured to provide a delay.
 7. The analog-to-digital converter of claim 4, wherein the time residue generator comprises: a ring-configured delay chain configured to generate a periodic square wave signal; and a comparator configured to resample a lag signal from the ring TDC with the periodic square wave signal.
 8. The analog-to-digital converter of claim 7, wherein the ring-configured delay chain is re-used in the third converter stage to avoid mismatch between the second converter stage and the third converter stage.
 9. The analog-to-digital converter of claim 4, wherein the time residue generator lacks edge selecting logic elements.
 10. The analog-to-digital converter of claim 1, wherein a coupling between the second converter stage and the third converter stage lacks a voltage-to-time converter.
 11. The analog-to-digital converter of claim 1, further comprising an inter-stage converter disposed between the first and second converter stages, the inter-stage converter being configured to convert between the voltage domain to a time domain.
 12. The analog-to-digital converter of claim 1, wherein: the inter-stage converter is configured to process the residue signal of the first converter stage such that a range of the residue signal matches a full scale of the second converter stage; the first converter stage comprises a continuous switching capacitor DAC (CDAC) and a voltage comparator; and the inter-stage converter comprises a voltage-to-time converter (VTC), the VTC having an input coupled to the voltage comparator.
 13. The analog-to-digital converter of claim 1, wherein the second converter stage comprises a ring time-to-digital converter (TDC).
 14. The analog-to-digital converter of claim 2, wherein the ring TDC and the VTC operate simultaneously.
 15. The analog-to-digital converter of claim 1, further comprising a background calibration loop to align the range of the residue signal of the first converter stage with the full scale of the second converter stage.
 16. The analog-to-digital converter of claim 1, wherein the inter-stage converter comprises a CDAC discharging-based VTC with CDAC switching timed by a lap delay of the ring TDC.
 17. The analog-to-digital converter of claim 1, wherein the residue signal has a residual voltage range equal to the full scale of the second converter stage.
 18. A system comprising a set of analog-to-digital converters, each analog-to-digital converter being configured in accordance with claim 1, wherein: the set of analog-to-digital converters are disposed in a parallel, time-interleaved arrangement; and the system further comprises a timing skew calibration circuit configured to determine timing skew via a comparison of a difference between sampling edges with an average value of sampling edge differences.
 19. The analog-to-digital converter of claim 1, further comprising: an inter-stage converter disposed between the first and second converter stages, the inter-stage converter being configured to convert the residual voltages from a voltage domain to a time domain; and a noise shaping circuit being configured to extract a time domain residue from the second converter stage, configured to convert the time domain residue to a voltage signal, configured to perform sigma-delta noise shaping, and configured to generate references to control the second converter stage.
 20. The analog-to-digital converter of claim 19, wherein: the first converter stage comprises capacitor DACs (CDACs) and comparators; the noise shaping circuit comprises a phase detector, a charge pump and a sigma-delta processing unit to extract and process a time domain residue and provide feedback for controlling the CDACs; and a low-pass filtered residue voltage is processed by the sigma-delta processing unit for noise shaping to update the references prior to a next fine quantizer conversion. 